电流型CMOS多值电路的设计

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic Pub Date : 1991-05-26 DOI:10.1109/ISMVL.1991.130718

Young-hoon Chang, J. T. Butler

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引用次数: 24

摘要

提出了一种基于成本表技术的多值电流型CMOS逻辑(CMCL)电路垂直划分算法。该算法是一种应用于与或树的启发式搜索技术(AO*算法)。它根据逻辑零的位置划分给定的函数。它比穷举搜索要快得多，同时提供了几乎同样好的实现。提出了一种成本表，它比以前的成本表更容易实现。

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The design of current mode CMOS multiple-valued circuits

A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizations that are almost as good. A cost-table that results in better realizations than obtained with a previous cost-table is proposed.<>

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[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

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