{"title":"FSK调制解调器优化NCO设计","authors":"Muhammad Asif, Zeeshan Ahmed","doi":"10.1109/SCONEST.2005.4382880","DOIUrl":null,"url":null,"abstract":"Paper highlights the design of a FSK modulator-demodulator on Verilog using Xilnix ISE with the careful memory efficient design of NCO. Reconfigurable radio design on FPGA has become the hot area of research these days. The design includes implementation details of Modulator and Decoder; decoder has been design in number of ways, paper briefly discusses the advantage and disadvantage of the approaches. Clock frequency is the only determining factor for the carrier frequency while the designed NCO creates accurate sine wave with low memory utilization. Memory requirement is as low as 4 bytes; hardware optimization is achieved using simplified multiplication and shift operation. Decoder can lock with wide variations of frequency digital PLL design is also considered.","PeriodicalId":447083,"journal":{"name":"2005 Student Conference on Engineering Sciences and Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Optimized NCO for FSK Modem\",\"authors\":\"Muhammad Asif, Zeeshan Ahmed\",\"doi\":\"10.1109/SCONEST.2005.4382880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Paper highlights the design of a FSK modulator-demodulator on Verilog using Xilnix ISE with the careful memory efficient design of NCO. Reconfigurable radio design on FPGA has become the hot area of research these days. The design includes implementation details of Modulator and Decoder; decoder has been design in number of ways, paper briefly discusses the advantage and disadvantage of the approaches. Clock frequency is the only determining factor for the carrier frequency while the designed NCO creates accurate sine wave with low memory utilization. Memory requirement is as low as 4 bytes; hardware optimization is achieved using simplified multiplication and shift operation. Decoder can lock with wide variations of frequency digital PLL design is also considered.\",\"PeriodicalId\":447083,\"journal\":{\"name\":\"2005 Student Conference on Engineering Sciences and Technology\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 Student Conference on Engineering Sciences and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCONEST.2005.4382880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 Student Conference on Engineering Sciences and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCONEST.2005.4382880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Paper highlights the design of a FSK modulator-demodulator on Verilog using Xilnix ISE with the careful memory efficient design of NCO. Reconfigurable radio design on FPGA has become the hot area of research these days. The design includes implementation details of Modulator and Decoder; decoder has been design in number of ways, paper briefly discusses the advantage and disadvantage of the approaches. Clock frequency is the only determining factor for the carrier frequency while the designed NCO creates accurate sine wave with low memory utilization. Memory requirement is as low as 4 bytes; hardware optimization is achieved using simplified multiplication and shift operation. Decoder can lock with wide variations of frequency digital PLL design is also considered.