高速128 Kbit MRAM核心，用于未来的通用存储器应用

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221207

A. Bette, J. DeBrosse, D. Gogl, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers, W. Obermaier, W. Reohr, H. Viehmann, W. Gallagher, G. Muller

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引用次数: 29

摘要

首次采用0.18 /spl mu/m, VDD=1.8 V，后端为Cu的逻辑处理技术，制作了128kb的MRAM(磁性随机存取存储器)测试芯片。本设计采用1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction)单元，并采用互补参考单元和可配置负载器件的对称高速传感架构。测试芯片测量和电路评估的外推预测5ns随机阵列读取访问时间和小于5ns写入脉冲宽度的随机写入操作。

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A high-speed 128 Kbit MRAM core for future universal memory applications

A 128 Kb MRAM (Magnetic Random Access Memory) test chip has been fabricated utilizing for the first time a 0.18 /spl mu/m, VDD=1.8 V, logic process technology with Cu backend of line. The presented design uses a 1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5 ns random array read access time and random write operations with <5 ns write pulse width.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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