E. Toh, G. Wang, L. Chan, G. Lo, D. Sylvester, C. Heng, G. Samudra, Y. Yeo
{"title":"一种互补的i- mos技术,具有SiGe通道和i-区域,用于增强冲击电离,击穿电压和性能","authors":"E. Toh, G. Wang, L. Chan, G. Lo, D. Sylvester, C. Heng, G. Samudra, Y. Yeo","doi":"10.1109/ESSDERC.2007.4430936","DOIUrl":null,"url":null,"abstract":"We report the first demonstration of silicon-germanium (SiGe) impact-ionization MOS (I-MOS) transistors that feature a SiGe channel and a SiGe impact-ionization region. The lower bandgap of SiGe as compared to Si contributes to higher electron and hole impact-ionization rates, leading to avalanche breakdown at a much reduced source voltage and enhanced device performance. Both n-and p-channel I-MOS devices were fabricated on Si0.7sGe0.25-on-insulator substrates using a CMOS-compatible process flow. Compared to Si I-MOS, the breakdown voltage of SiGe I-MOS is reduced by ~1 V along with the doubling of the drive current and transconductance. The subthreshold swing is also improved. Excellent subthreshold swings of 2.88 mV/decade and 3.24 mV/decade are achieved for the n-and p-channel SiGe I-MOS devices, respectively.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A complementary-I-MOS technology featuring SiGe channel and i-region for enhancement of impact-ionization, breakdown voltage, and performance\",\"authors\":\"E. Toh, G. Wang, L. Chan, G. Lo, D. Sylvester, C. Heng, G. Samudra, Y. Yeo\",\"doi\":\"10.1109/ESSDERC.2007.4430936\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report the first demonstration of silicon-germanium (SiGe) impact-ionization MOS (I-MOS) transistors that feature a SiGe channel and a SiGe impact-ionization region. The lower bandgap of SiGe as compared to Si contributes to higher electron and hole impact-ionization rates, leading to avalanche breakdown at a much reduced source voltage and enhanced device performance. Both n-and p-channel I-MOS devices were fabricated on Si0.7sGe0.25-on-insulator substrates using a CMOS-compatible process flow. Compared to Si I-MOS, the breakdown voltage of SiGe I-MOS is reduced by ~1 V along with the doubling of the drive current and transconductance. The subthreshold swing is also improved. Excellent subthreshold swings of 2.88 mV/decade and 3.24 mV/decade are achieved for the n-and p-channel SiGe I-MOS devices, respectively.\",\"PeriodicalId\":103959,\"journal\":{\"name\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2007.4430936\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430936","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A complementary-I-MOS technology featuring SiGe channel and i-region for enhancement of impact-ionization, breakdown voltage, and performance
We report the first demonstration of silicon-germanium (SiGe) impact-ionization MOS (I-MOS) transistors that feature a SiGe channel and a SiGe impact-ionization region. The lower bandgap of SiGe as compared to Si contributes to higher electron and hole impact-ionization rates, leading to avalanche breakdown at a much reduced source voltage and enhanced device performance. Both n-and p-channel I-MOS devices were fabricated on Si0.7sGe0.25-on-insulator substrates using a CMOS-compatible process flow. Compared to Si I-MOS, the breakdown voltage of SiGe I-MOS is reduced by ~1 V along with the doubling of the drive current and transconductance. The subthreshold swing is also improved. Excellent subthreshold swings of 2.88 mV/decade and 3.24 mV/decade are achieved for the n-and p-channel SiGe I-MOS devices, respectively.