数据代码生成占DSP应用的主导地位，以FPGA为目标

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI:10.1109/IWRSP.1998.676686

J. Dalcolmo, R. Lauwereins, M. Adé

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引用次数: 18

摘要

GRAPE快速原型和设计环境的VHDL代码生成器已经扩展到支持更广泛的数据主导应用程序。我们描述了在fpga上实现CSDF应用程序的方法，包括在fpga上单独或与DSP处理器一起用于任务通信和调度的自动代码生成。讨论了实现选择，并与手工代码生成进行了比较。

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Code generation of data dominated DSP applications for FPGA targets

The VHDL code generator of the GRAPE rapid prototyping and design environment has been extended to support a much wider range of data dominated applications. We describe the approach taken to implement CSDF applications on FPGAs, including the automatic code generation for task communication and scheduling on FPGAs alone or in conjunction with DSP processors. The implementation choices are discussed, and a comparison to manual code generation is made.

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Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)

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