存储设备的未来展望

Kinam Kim, Donggun Park
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引用次数: 3

摘要

只提供摘要形式。自70年代初硅存储器件发明以来,硅存储器件以前所未有的速度发展,导致存储器件的存储容量呈指数级增长,目前DRAM达到60 nm节点的1Gb密度,NAND闪存达到50 nm节点的16 Gb密度。在过去30年硅存储器件的发展过程中,硅存储器件的开关面临着初始阶段似乎很难克服的关键挑战。但这些挑战最终通过合适的经济有效的解决方案得以解决,并且一些挑战将硅存储技术从简单和常见的平面技术转变为复杂和多样化的技术,如平面晶体管和三维电容器以及最近的三维晶体管和三维电容器等。然而,随着硅技术进一步深入纳米尺度,硅存储器件将面临许多严峻的挑战,这些挑战来自晶体管尺度的极限和由于技术复杂性而导致的制造成本不断增加的制造边际。尽管未来硅存储器件似乎没有统一的解决方案,但大多数硅存储领域的专家认为,硅存储技术将给出正确的解决方案,直到20nm节点,晶体管只包含少量电子,这被认为是一个实用的限制,以避免随机电报噪声引起的噪声误差,1/根数统计引起的信号变化,以及由于传播线的粗糙边缘和厚度变化等引起的波动。此外,关于深度纳米级存储器件还有许多未知之处。因此,本文将主要从半导体存储器件的基础和关键特征、关键技术和设计等方面讨论半导体存储器件面临的主要挑战及其可能的解决方案,以找到未来半导体存储器件的正确方向。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The future outlook of memory devices
Summary form only given. Since the inventions of silicon memory devices at early 70's, silicon memory devices have been advanced with unprecedented pace which results in exponential growth of storage capacity of memory devices, and now they reach to 1Gb density with 60 nm node for DRAM and 16 Gb density with 50 nm node for NAND Flash. During the evolution of silicon memory devices for the last 3 decades, silicon memory devices on-and-off faced critical challenges which seemed to be very difficult to surmount at initial stage, but those challenges were eventually cleared by appropriate cost-effective solutions and some of challenges paradigm shifted silicon memory technologies from simple and common planar technology to complicated and diversified technologies such as planar transistor with 3-D capacitor and recently 3-D transistor with 3-D capacitor and etc. However, as the silicon technologies further enter deep nano-scale dimensions, silicon memory devices will encounter much critical challenges originated from ultimate limit of the transistor scaling and shallow margins in manufacturing due to ever-increasing fabrication costs resulting from technical complexities. Although there seems to be no unanimous solutions for silicon memory devices in future, most of experts working in silicon memory area, however, believe that silicon memory technology will be given right solutions down to a 20 nm node where a transistor contains only a small number of electrons, which is believed to be a practical limit to avoid noise errors owing to random telegraph noises, signal variations due to 1/radicn statistics, and fluctuations due to both rough edges of propagating lines and thickness variations and so forth. In addition, there are still many unknowns about the deep nano scaled memory devices. Thus, in this paper, in order to find the right directions of future semiconductor memory devices, key challenges and their possible solutions will be mainly discussed in views of basics and key features of semiconductor memory devices, key technologies and designs.
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