Luca Amati, C. Bolchini, L. Frigerio, F. Salice, B. Eklow, Arnold Suvatne, E. Brambilla, F. Franzoso, Michele Martin
{"title":"一种功能诊断的增量方法","authors":"Luca Amati, C. Bolchini, L. Frigerio, F. Salice, B. Eklow, Arnold Suvatne, E. Brambilla, F. Franzoso, Michele Martin","doi":"10.1109/DFT.2009.29","DOIUrl":null,"url":null,"abstract":"This paper presents a methodology for an incremental approach to functional fault diagnosis of complex boards, used to identify candidate failing components based on the results of the executed tests, once a misbehavior has been detected but not localized. The proposal aims at reducing both time and effort during the diagnostic phase, by executing a subset of the available tests, analyzing the achieved results, and then supporting the operator by suggesting what tests should be run next, to identify the faulty component, should the already gathered information be insufficient. A methodology has been defined to analyze the available results, and to evaluate the effectiveness of the remaining tests to find the most probable cause of failure in a reduced number of additional test runs. The approach has been validated on a portion of a real life board and other circuits, to tune parameters and to evaluate the performance of the proposed methodology.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"An Incremental Approach to Functional Diagnosis\",\"authors\":\"Luca Amati, C. Bolchini, L. Frigerio, F. Salice, B. Eklow, Arnold Suvatne, E. Brambilla, F. Franzoso, Michele Martin\",\"doi\":\"10.1109/DFT.2009.29\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a methodology for an incremental approach to functional fault diagnosis of complex boards, used to identify candidate failing components based on the results of the executed tests, once a misbehavior has been detected but not localized. The proposal aims at reducing both time and effort during the diagnostic phase, by executing a subset of the available tests, analyzing the achieved results, and then supporting the operator by suggesting what tests should be run next, to identify the faulty component, should the already gathered information be insufficient. A methodology has been defined to analyze the available results, and to evaluate the effectiveness of the remaining tests to find the most probable cause of failure in a reduced number of additional test runs. The approach has been validated on a portion of a real life board and other circuits, to tune parameters and to evaluate the performance of the proposed methodology.\",\"PeriodicalId\":405651,\"journal\":{\"name\":\"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2009.29\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2009.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a methodology for an incremental approach to functional fault diagnosis of complex boards, used to identify candidate failing components based on the results of the executed tests, once a misbehavior has been detected but not localized. The proposal aims at reducing both time and effort during the diagnostic phase, by executing a subset of the available tests, analyzing the achieved results, and then supporting the operator by suggesting what tests should be run next, to identify the faulty component, should the already gathered information be insufficient. A methodology has been defined to analyze the available results, and to evaluate the effectiveness of the remaining tests to find the most probable cause of failure in a reduced number of additional test runs. The approach has been validated on a portion of a real life board and other circuits, to tune parameters and to evaluate the performance of the proposed methodology.