K. Aizawa, Y. Egi, T. Hamamoto, M. Hatori, J. Yamazaki
{"title":"用于传感器上压缩的图像传感器","authors":"K. Aizawa, Y. Egi, T. Hamamoto, M. Hatori, J. Yamazaki","doi":"10.1109/CAMP.1995.521014","DOIUrl":null,"url":null,"abstract":"We present a novel image sensor on which image signal can be compressed. Since image signal is compressed on an imager plane by making use of parallel nature of image signals, the amount of signal read out from the imager can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging and very high resolution real time imaging; the very high bandwidth is the fundamental limitation for feasibility of those high pixel rate sensors and processing systems. Analog circuits have been designed both for processing in each pixel and for controlling entire data rate. A first prototype of a VLSI chip has been fabricated. Some results of the examination are shown in this paper.","PeriodicalId":277209,"journal":{"name":"Proceedings of Conference on Computer Architectures for Machine Perception","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"An image sensor for on-sensor-compression\",\"authors\":\"K. Aizawa, Y. Egi, T. Hamamoto, M. Hatori, J. Yamazaki\",\"doi\":\"10.1109/CAMP.1995.521014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a novel image sensor on which image signal can be compressed. Since image signal is compressed on an imager plane by making use of parallel nature of image signals, the amount of signal read out from the imager can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging and very high resolution real time imaging; the very high bandwidth is the fundamental limitation for feasibility of those high pixel rate sensors and processing systems. Analog circuits have been designed both for processing in each pixel and for controlling entire data rate. A first prototype of a VLSI chip has been fabricated. Some results of the examination are shown in this paper.\",\"PeriodicalId\":277209,\"journal\":{\"name\":\"Proceedings of Conference on Computer Architectures for Machine Perception\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Conference on Computer Architectures for Machine Perception\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAMP.1995.521014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Conference on Computer Architectures for Machine Perception","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAMP.1995.521014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present a novel image sensor on which image signal can be compressed. Since image signal is compressed on an imager plane by making use of parallel nature of image signals, the amount of signal read out from the imager can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging and very high resolution real time imaging; the very high bandwidth is the fundamental limitation for feasibility of those high pixel rate sensors and processing systems. Analog circuits have been designed both for processing in each pixel and for controlling entire data rate. A first prototype of a VLSI chip has been fabricated. Some results of the examination are shown in this paper.