一个1.8 V, 1 MS/s, 85 dB信噪比2+2 mash /spl Sigma//spl Delta/调制器，参考电压/spl plusmn/0.9 V

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221165

Kye-Shin Lee, F. Maloberti

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引用次数: 3

摘要

采用减摆结构实现了一个1.8 V、1 MS/s、85 dB信噪比2+2 mash /spl Sigma//spl Delta/调制器，参考电压为/spl plusmn/0.9 V。这种结构将所有积分器的输出摆幅限制在参考电压的一半以内。因此，在不降低调制器性能的情况下，即使具有高参考电压，也可以实现低电压和高速操作。电路采用CMOS 0.35 /spl mu/m工艺，芯片尺寸为2.5/spl times/2.5 mm/sup 2/。

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A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage

A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage is realized by using the swing reduction structure. This structure limits the output swing of all the integrators within half the reference voltage. Thus, low voltage and high speed operation is possible with even high reference voltage without degrading the performance of the modulator. The circuit is fabricated in CMOS 0.35 /spl mu/m process with chip size of 2.5/spl times/2.5 mm/sup 2/.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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