实现IPC性能(仍然是可扩展性的基础)

Proceedings. The Sixth Workshop on Hot Topics in Operating Systems (Cat. No.97TB100133) Pub Date : 1997-05-05 DOI:10.1109/HOTOS.1997.595177

J. Liedtke, Kevin Elphinstone, S. Schönberg, Hermann Härtig, G. Heiser, N. Islam, T. Jaeger

{"title":"实现IPC性能(仍然是可扩展性的基础)","authors":"J. Liedtke, Kevin Elphinstone, S. Schönberg, Hermann Härtig, G. Heiser, N. Islam, T. Jaeger","doi":"10.1109/HOTOS.1997.595177","DOIUrl":null,"url":null,"abstract":"Extensibility can be based on cross-address-space interprocess communication (IPC) or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 microkernel on Intel Pentium, Mips R4600 and DEC Alpha processors. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.","PeriodicalId":176246,"journal":{"name":"Proceedings. The Sixth Workshop on Hot Topics in Operating Systems (Cat. No.97TB100133)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"82","resultStr":"{\"title\":\"Achieved IPC performance (still the foundation for extensibility)\",\"authors\":\"J. Liedtke, Kevin Elphinstone, S. Schönberg, Hermann Härtig, G. Heiser, N. Islam, T. Jaeger\",\"doi\":\"10.1109/HOTOS.1997.595177\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Extensibility can be based on cross-address-space interprocess communication (IPC) or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 microkernel on Intel Pentium, Mips R4600 and DEC Alpha processors. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.\",\"PeriodicalId\":176246,\"journal\":{\"name\":\"Proceedings. The Sixth Workshop on Hot Topics in Operating Systems (Cat. No.97TB100133)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"82\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. The Sixth Workshop on Hot Topics in Operating Systems (Cat. No.97TB100133)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTOS.1997.595177\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. The Sixth Workshop on Hot Topics in Operating Systems (Cat. No.97TB100133)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTOS.1997.595177","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 82

摘要

可扩展性可以基于跨地址空间进程间通信(IPC)，也可以基于将特定于应用程序的模块移植到操作系统中。为了比较这两种方法，我们需要探索两种模型的最佳可实现性能。本文报道了L4微内核在Intel Pentium、Mips R4600和DEC Alpha处理器上实现的跨地址空间通信性能。直接成本从45个周期(Alpha)到121个周期(Pentium)不等。由于只需要L1缓存的2.3% (Pentium)，因此预计平均间接成本不会高得多。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Achieved IPC performance (still the foundation for extensibility)

Extensibility can be based on cross-address-space interprocess communication (IPC) or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 microkernel on Intel Pentium, Mips R4600 and DEC Alpha processors. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.

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Proceedings. The Sixth Workshop on Hot Topics in Operating Systems (Cat. No.97TB100133)

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