32nm高k金属栅极应用处理器,GHz多核CPU

Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang
{"title":"32nm高k金属栅极应用处理器,GHz多核CPU","authors":"Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang","doi":"10.1109/ISSCC.2012.6176980","DOIUrl":null,"url":null,"abstract":"Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"A 32nm high-k metal gate application processor with GHz multi-core CPU\",\"authors\":\"Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang\",\"doi\":\"10.1109/ISSCC.2012.6176980\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.\",\"PeriodicalId\":255282,\"journal\":{\"name\":\"2012 IEEE International Solid-State Circuits Conference\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2012.6176980\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2012.6176980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18

摘要

三星的下一代32nm双核/四核Exynos™处理器在同一个芯片上集成了2或4个ARM-v7A架构内核,2端口DRAM控制器以及众多多媒体加速器和连接块。它是一款应用处理器(AP),旨在覆盖各种移动应用程序,处理前所未有的数据处理吞吐量和多媒体性能,而不会牺牲电池寿命或超过热功耗。架构图如图12.1.1所示,四核配置的芯片照片如图12.1.7所示。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 32nm high-k metal gate application processor with GHz multi-core CPU
Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信