Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang
{"title":"32nm高k金属栅极应用处理器,GHz多核CPU","authors":"Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang","doi":"10.1109/ISSCC.2012.6176980","DOIUrl":null,"url":null,"abstract":"Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"A 32nm high-k metal gate application processor with GHz multi-core CPU\",\"authors\":\"Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang\",\"doi\":\"10.1109/ISSCC.2012.6176980\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.\",\"PeriodicalId\":255282,\"journal\":{\"name\":\"2012 IEEE International Solid-State Circuits Conference\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2012.6176980\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2012.6176980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 32nm high-k metal gate application processor with GHz multi-core CPU
Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.