SRAM designs for 5nm node and beyond: Opportunities and challenges

The rising demand for battery-powered devices is the key driver for continued density scaling and improved power in SoCs. Along with advantages, random VT variation and interconnect RC delay is increased due to the continual scaling of physical dimensions, which seriously degrades SRAM performances, limits VMIN, and makes SRAM less energy efficient. Although FinFET technology can offer a respectable source channel effects (SCEs) and superior VT variation, the competing between channel length (Lg), sidewall spacers, and source/drain (S/D) contacts imposed by contacted gate pitch (CGP) scaling remains unchanged. In this paper, we will present a holistic approach for 6T-SRAM designs using gate-all-around (GAA) transistors, which will firmly address process integrations and circuit aspects arising at the 5nm node. Several read and write assist techniques including wordline (WL) delayed overdrive, VDD collapse and negative bitline (BL) will be exclusively investigated to enable low VMIN and high-performance SRAMs.