{"title":"利用FPGA技术实现真实编码的粒子群算法","authors":"Mohamed Sadok Ben Ameur, A. Sakly, A. Mtibaa","doi":"10.1109/STA.2014.7086765","DOIUrl":null,"url":null,"abstract":"In this paper, a parallel PSO algorithm structure based on (FSM) Finite state machine is proposed. The use of FPGA (Field Programmable Gate Array) has shown many advantages over other circuits based on swarm intelligence mainly due to its simplicity and robustness to solve mathematic problems that contain several variables. This paper evaluates the performance of the PSO that's why we developed a hardware architecture that accelerates its execution performance by updating velocity and position of particles. The fitness evaluation module is implemented and mapped into FPGA reconfigurable hardware. The accelerated execution performance of the proposed architecture is demonstrated on standard mathematical functions as well as on a real coded problem.","PeriodicalId":125957,"journal":{"name":"2014 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Implementation of real coded PSO algorithms using FPGA technology\",\"authors\":\"Mohamed Sadok Ben Ameur, A. Sakly, A. Mtibaa\",\"doi\":\"10.1109/STA.2014.7086765\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a parallel PSO algorithm structure based on (FSM) Finite state machine is proposed. The use of FPGA (Field Programmable Gate Array) has shown many advantages over other circuits based on swarm intelligence mainly due to its simplicity and robustness to solve mathematic problems that contain several variables. This paper evaluates the performance of the PSO that's why we developed a hardware architecture that accelerates its execution performance by updating velocity and position of particles. The fitness evaluation module is implemented and mapped into FPGA reconfigurable hardware. The accelerated execution performance of the proposed architecture is demonstrated on standard mathematical functions as well as on a real coded problem.\",\"PeriodicalId\":125957,\"journal\":{\"name\":\"2014 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/STA.2014.7086765\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/STA.2014.7086765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of real coded PSO algorithms using FPGA technology
In this paper, a parallel PSO algorithm structure based on (FSM) Finite state machine is proposed. The use of FPGA (Field Programmable Gate Array) has shown many advantages over other circuits based on swarm intelligence mainly due to its simplicity and robustness to solve mathematic problems that contain several variables. This paper evaluates the performance of the PSO that's why we developed a hardware architecture that accelerates its execution performance by updating velocity and position of particles. The fitness evaluation module is implemented and mapped into FPGA reconfigurable hardware. The accelerated execution performance of the proposed architecture is demonstrated on standard mathematical functions as well as on a real coded problem.