Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs

Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures