具有完整栅极后植入方案的低成本CMOS工艺

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI:10.1109/ESSDERC.1997.194450

M. Kerber, U. Schwalke, R. Heinrich

{"title":"具有完整栅极后植入方案的低成本CMOS工艺","authors":"M. Kerber, U. Schwalke, R. Heinrich","doi":"10.1109/ESSDERC.1997.194450","DOIUrl":null,"url":null,"abstract":"A low cost CMOS process flow is proposed which unifies all implantations to form NMOS and PMOS devices in a single mask step for each transistor type. This reduces the total mask count by three and hence cost and processing time accordingly. Experimental results demonstrate electrical performance comparable to conventional CMOS technologies.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme\",\"authors\":\"M. Kerber, U. Schwalke, R. Heinrich\",\"doi\":\"10.1109/ESSDERC.1997.194450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low cost CMOS process flow is proposed which unifies all implantations to form NMOS and PMOS devices in a single mask step for each transistor type. This reduces the total mask count by three and hence cost and processing time accordingly. Experimental results demonstrate electrical performance comparable to conventional CMOS technologies.\",\"PeriodicalId\":424167,\"journal\":{\"name\":\"27th European Solid-State Device Research Conference\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.1997.194450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.1997.194450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

提出了一种低成本的CMOS工艺流程，该流程可以在单个掩模步骤中统一所有植入，形成每种晶体管类型的NMOS和PMOS器件。这减少了总掩码数三个，因此相应的成本和处理时间。实验结果表明，其电性能与传统CMOS技术相当。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme

A low cost CMOS process flow is proposed which unifies all implantations to form NMOS and PMOS devices in a single mask step for each transistor type. This reduces the total mask count by three and hence cost and processing time accordingly. Experimental results demonstrate electrical performance comparable to conventional CMOS technologies.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

27th European Solid-State Device Research Conference

自引率

0.00%

发文量