用于高转换率升压稳压器的单电感级联级拓扑结构

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI:10.1109/ICCD.2016.7753331

K. Z. Ahmed, S. Mukhopadhyay

{"title":"用于高转换率升压稳压器的单电感级联级拓扑结构","authors":"K. Z. Ahmed, S. Mukhopadhyay","doi":"10.1109/ICCD.2016.7753331","DOIUrl":null,"url":null,"abstract":"A single-inductor-cascaded-stage boost regulator topology is presented that time-multiplexes a single inductor using one-nFET-two-pFET power stage and a bias-gated Pulse-Frequency Modulation controller to achieve high conversion ratio. A test-chip in 130nm CMOS demonstrates 120× conversion using a single inductor while consuming 140nA bias current.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A single-inductor-cascaded-stage topology for high conversion ratio boost regulator\",\"authors\":\"K. Z. Ahmed, S. Mukhopadhyay\",\"doi\":\"10.1109/ICCD.2016.7753331\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-inductor-cascaded-stage boost regulator topology is presented that time-multiplexes a single inductor using one-nFET-two-pFET power stage and a bias-gated Pulse-Frequency Modulation controller to achieve high conversion ratio. A test-chip in 130nm CMOS demonstrates 120× conversion using a single inductor while consuming 140nA bias current.\",\"PeriodicalId\":297899,\"journal\":{\"name\":\"2016 IEEE 34th International Conference on Computer Design (ICCD)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 34th International Conference on Computer Design (ICCD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2016.7753331\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 34th International Conference on Computer Design (ICCD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2016.7753331","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

提出了一种单电感级联升压调节器拓扑结构，该拓扑结构利用一个nfet -两个pfet功率级和一个偏置门控脉冲调频控制器对单个电感进行时间复用，以实现高转换率。130nm CMOS测试芯片在消耗140nA偏置电流的情况下，使用单个电感实现了120x转换。

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A single-inductor-cascaded-stage topology for high conversion ratio boost regulator

A single-inductor-cascaded-stage boost regulator topology is presented that time-multiplexes a single inductor using one-nFET-two-pFET power stage and a bias-gated Pulse-Frequency Modulation controller to achieve high conversion ratio. A test-chip in 130nm CMOS demonstrates 120× conversion using a single inductor while consuming 140nA bias current.

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2016 IEEE 34th International Conference on Computer Design (ICCD)

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