10gb /s兼容sonet的CMOS收发器，具有低串扰和固有抖动

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332649

H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger, T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. de Mercey, H. Geib

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引用次数: 29

摘要

采用0.13 /spl mu/m标准CMOS的单片全速率收发器功耗小于1w。通过在VCO中使用特殊的电源概念和陷波高q电感器，IC实现了0.2 ps的rms抖动。在7 GHz BW下灵敏度为20 mV的限制放大器使CDR能够以<10/sup -12/的误码率恢复数据。

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A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter

A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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