基于机器学习的超大规模集成电路技术开发设计与系统技术协同优化灵敏度预测

Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin
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引用次数: 5

摘要

随着技术节点的发展,几何音高缩放开始放缓。为了保持摩尔定律的趋势,设计技术协同优化(DTCO)和系统技术协同优化(STCO)被一起引入,使用基音缩放、图像化和新颖的3D单元结构(即互补场效应管(CFET))继续扩展到5nm以上。然而,考虑到成本、各种标准单元(SDC)高度、SDC架构、设计规则和后端线(BEOL)设置,需要进行大量的DTCO和STCO迭代来继续进行块级面积缩放。标准单元设计、设计规则优化和块级面积评估之间不断增长的周转时间(TAT)成为DTCO和STCO探索的主要瓶颈之一。在这项工作中,我们提出了一种基于机器学习技术的DTCO和STCO灵敏度预测方法,以提高DTCO和STCO在块级区域上的探测性能。我们研究并提取了块级设计、SDCs、设计规则和beol的关键指标。我们使用机器学习模型来预测在调整设计规则和不同SDC集(即不同单元高度,常规FET, cfeet等)的beol时最小有效块级面积的灵敏度。我们首先证明,该模型在预测各种SDC集、设计规则和BEOL设置的块级区域灵敏度时,测试集的平均绝对误差(MAE)达到4.05 ×10−3。然后,我们证明了所提出的模型成功地捕获了跨多个SDC集和设计的新SDC集和新BEOL设置的块级区域灵敏度,分别为3.3 ×10-2and 6 ×10−3MAEs。最后,在预测新设计的鲁棒性实验中,所提出的建模方法平均达到5.75 ×10−2MAE。与传统的DTCO和STCO勘探流程相比,所提出的框架提供了100倍以上的加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning
As technology nodes evolve, geometric pitch scaling starts to slow down. In order to retain the trend of the Moore's Law, Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) are introduced together to continue scaling beyond 5nm using pitch scaling, patterning, and novel 3D cell structures (i.e., Complementary-FET (CFET)). However, numerous DTCO and STCO iterations are needed to continue block-level area scaling with considerations of cost, various standard cell (SDC) heights, SDC architectures, design rules, and back end of line (BEOL) settings. The growing turnaround time (TAT) among standard cell design, design rule optimization, and block-level area evaluation becomes one of the major bottlenecks in DTCO and STCO explorations. In this work, we propose a DTCO and STCO sensitivity prediction method to improve the performance of DTCO and STCO explorations on block-level area using machine learning techniques. We study and extract the key metrics of block-level designs, SDCs, design rules, and BEOLs. We use a machine learning model to predict the sensitivity of minimum valid block-level area when tuning the design rules and BEOLs with various SDC sets (i.e., different cell heights, Conventional FET, CFET, etc.). We firstly demonstrate that the proposed model achieves 4.05 ×10−3 mean absolute error (MAE) for testing sets to predict block-level area sensitivity of various SDC sets, design rules, and BEOL settings. Then, we show that the proposed model successfully captures the block-level area sensitivity of new SDC sets and new BEOL settings across multiple SDC sets and designs with 3.3 ×10-2and 6 ×10−3MAEs, respectively. Lastly, the proposed modeling approach achieves 5.75 ×10−2MAE on average in the robustness experiment on predicting new designs. The proposed framework provides more than 100× speedups compared to conventional DTCO and STCO exploration flows.
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