用于电力线通信的全数字扩频调制解调器的信号处理专用集成电路

K. Dostert
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引用次数: 1

摘要

通过扩频技术的应用,低压配电网成为可靠、通用的数字数据链路。在对适当的信号方案进行简短的回顾之后,本文将概述导致构建ASIC的基本思想。由于使用通用数字信号处理器(DSP)既不可行也不划算,因此必须采取这一步骤。将发送器部分设计成ASIC相对容易。具有复位到零功能的廉价计数器作为精确和快速信号合成的核心元件。信号选择和定时控制由板载微控制器完成。接收机信号处理的解决方案较为复杂。需要一个基于MAC结构(乘法和累加)进行相关运算的快速信号处理前端。所述的板载微控制器执行位判断、串行数据传输以及定时和控制功能。调查显示,8位的字长在一个典型的电力线调制解调器的发送和接收部分是足够的。最后,ASIC必须包含以下功能块:一个8位MAC单元,至少有四个独立的32位累加器,一个微控制器接口,一个9位可编程计数器,以及一个时钟和控制单元。根据概述的方案,asic在1993年春使用0.8 /spl mu/m BiCMOS全定制工艺设计和制造。测试显示,在12 MHz的全速工作速度下,功耗低于5 mW。半双工调制解调器正在建设中,具有不同的信号方案,数据速率高达2400比特/秒。首次测量显示,典型室内安装的误码率在10/sup -5/范围内。进一步的工作将集中在户外应用,如远程抄表以及对消费者房屋的控制和监督
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A signal processing ASIC for an all digital spread spectrum modem for power line communications
Through the use of spread spectrum techniques low voltage electrical power distribution networks become reliable and universal digital data links. After a short review of appropriate signalling schemes the paper will outline the basic ideas leading to the construction of an ASIC. It is shown that this step has to be taken because the use of general purpose digital signal processors (DSP) is neither feasible nor cost-effective. The design of the transmitter section into an ASIC is relatively easy. An inexpensive counter with a reset-to-zero feature operates as the core element for precise and fast signal synthesis. Signal selection and timing control are performed by an on-board microcontroller. The solution for receiver signal processing is more complicated. A fast signal processing front end is needed which does correlation operations based on a MAC structure (multiply and accumulate). The mentioned on-board microcontroller performs bit decision, serial data transfer as well as timing and control functions. Investigations revealed that a word length of 8 bit is sufficient in the transmitter as well as in the receiver section of a typical power line modem. Finally the ASIC has to contain the following functional blocks: an 8 bit MAC unit with at least four separate 32 bit accumulators, a microcontroller interface, a 9 bit programmable counter, and a clocking and control unit. ASICs according to the outlined scheme were designed and fabricated in spring 1993 using a 0.8 /spl mu/m BiCMOS full custom process. Testing revealed a power consumption of less than 5 mW at the full operating speed of 12 MHz. Half-duplex modems are under construction with different signalling schemes for data rates up to 2400 bits/s. First measurements revealed a bit error rate at typical indoor installations in the range of 10/sup -5/. Further work will concentrate on outdoor applications such as remote meter reading as well as control and supervision of consumer's premises.<>
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