一种用于嵌入式soc的低功耗快速唤醒闪存系统

2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI:10.1109/ICICDT.2017.7993516

Karthik Ramanan, Jacob Williams

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引用次数: 2

摘要

本文描述了一种系统级方法来实现闪存系统，该系统在待机模式下消耗非常小的电流(小于1µa)，并且可以快速唤醒(~ 1µs)以进行随机访问读取操作。本文主要讨论如何划分模拟电路和其他闪存组件来实现这些规格。此外，还说明了各种电路的设计注意事项。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low power fast wakeup flash memory system for embedded SOCs

This paper describes a system level approach to achieve a flash memory system that would consume very little current (less than a 1µA) in standby mode and would wake up fast (∼1µs) for a random-access read operation. The paper mainly focuses how analog circuits and other flash memory components can be partitioned to achieve these specifications. In addition, design considerations for various circuits have also been illustrated.

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2017 IEEE International Conference on IC Design and Technology (ICICDT)

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