An Efficient Hardware Design for Combined AES and AEGIS

This paper presents an integrated design of AES, the block cipher standard and AEGIS, an AES based authenticated encryption. Our design tries to exploit the common functionalities of AES and AEGIS to achieve both confidentiality as well as confidentiality and authenticity together. The proposed design provides a cost-effective implementation on various FPGA platforms, and it achieves both the goals by using a minimum amount of extra resources compared to the stand-alone AES and AEGIS design. The performance of our design implementation has been compared with the similar design work, and it has been shown that the throughput and frequency of our design outperform the best result available in the literature.