Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodes in Digital Circuits

This paper presents a method to mitigate Negative Bias Temperature Instability (NBTI) in digital circuits. Since effect of NBTI strongly depends on digital logic value of internal nodes, this method uses internal nodes control (INC) method to reduce NBTI-critical transistors. There are some internal nodes in digital circuits that are under severe NBTI. This method at first, identifies NBTI-critical internal nodes in critical and non-critical paths by calculating probability of being under NBTI stress. Second, it eliminates these internal nodes by combining NBTI-sensitive gates and their driver gates, generating a new complex gate. These complex gates have the same logic and remove any NBTI-critical transistors. The proposed method reduces NBTI in combinational and sequential CMOS circuits and increases their lifetime. Experimental results on ISCAS'89 benchmark circuits show that NBTI-critical transistors, NBTI-induced delay degradation and the number of circuit's transistors are decreased about 86.1%, 15.12% and 4.3%, respectively. However, this method imposes area overhead of 0.2% for the investigated circuits.