基于FPGA的片上网络原型设计自动化

2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) Pub Date : 2019-08-01 DOI:10.1109/DISCOVER47552.2019.9008005

Divyansh Mahajan, Swarali Patil, Wagh Vipul Shashikant, Mohit Dangayach, P. V. Bhanu, J. Soumya

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引用次数: 1

摘要

本文讨论了在优化的片上网络(NoC)设计的综合中使用的自动化过程。NoC的拓扑结构和网络中的节点数量可以根据用户的需求而变化。自动化的目的是加快设计过程，执行资源利用率分析，并在FPGA上实现具有用户指定的网络大小的任何拓扑结构的原型NoC架构。这是通过开源语言Python 3.0和Xilinx Vivado工具(2014.4)提供的TCL控制台实现的。所得结果对于测试NoC和在FPGA板上进行原型设计是有用的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design Automation of Network-on-Chip Prototype on FPGA

This paper addresses the automation process used in the synthesis of an optimized Network-on-Chip (NoC) design. The topology of a NoC and the number of nodes in the network may vary depending on the user requirement. The aim of automation is to faster the design process, perform resource utilization analysis, and prototype NoC architecture on to FPGA for any topology with the network size specified by user. This has been achieved through the open source language Python 3.0, and TCL console provided by Xilinx Vivado tool (2014.4). The results obtained are useful for testing NoC and prototyping it on to FPGA boards.

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2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)

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