基于吠陀数学的方形和立方体结构的FPGA实现

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI:10.1109/ISES.2018.00012

Sampada Barve, S. Raveendran, Charudatta Korde, T. Panigrahi, Nithin Kumar Y. B., Vasantha M. H.

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引用次数: 4

摘要

在数字信号处理的各种应用中，平方和立方单元具有重要的意义。本文提出了一种基于安约约达沙克比吠陀数学经典和Dwandwa瑜伽(双工)的新的正方形结构。此外，还提出了一种基于所建议的方形和《阿鲁毗陀经》的新的立方体结构。在kintex 7 FPGA板上实现了8位和16位的平方单元和8位的立方单元。对于8位输入，所提出的正方形的功率延迟积为106.99和45.65，而立方体的功率延迟积为444.47。

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FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics

Squaring and cubing units have importance in various applications in digital signal processing. This paper proposes new squaring architectures based on vedic mathematics sutra of Antyayordashakepi and Dwandwa Yoga (Duplex). Further a new cube architecture based on proposed square and Anurupya sutra is also proposed. The squaring units were implemented for bit size of 8 and 16 while cube was implemented for bit size of 8 on kintex 7 FPGA board. Proposed squarers provided with power delay product of 106.99 and 45.65 whereas cube had power delay product of 444.47 for 8 bits of input.

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2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

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