取代传统雷达的数字色散延迟线

D.C. Earl, D. Moulin, R.L. Landran, H.G. Leney, R. Rifkin
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引用次数: 0

摘要

一些传统的相控阵雷达使用模拟色散延迟线来扩展和压缩其调频啁啾波形。这些基于声学的设备通常不再可用。本文介绍了一种功能等效的模拟延迟线的数字替代设计。考虑了各种设计选项,包括中频与基带处理,时域与频域滤波,COTS板与定制asic。解决了系统设计中的动态范围、啁啾脉冲响应设计、延迟线处理延迟以及收发端不匹配的影响等问题。板级设计的主要挑战是在固有的短模拟延迟线延迟内满足数字信号处理的计算需求。这最终需要开发定制的VLSI信号处理芯片。130万晶体管ASIC芯片执行1024分路有限脉冲响应(FIR)滤波器,运行在估计2 Msps。ASIC的可配置架构允许使用FIR滤波器抽头的数量来交换采样率,并且可以在其他雷达或通信系统中使用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Digital dispersive delay line replacement for legacy radars
Some legacy phased array radars use analog dispersive delay lines to expand and compress their FM chirp waveforms. These acoustic-based devices are often no longer available. This paper describes the design of a functionally equivalent digital replacement for one of these analog delay lines. Various design options were considered including IF versus baseband processing, time domain versus frequency domain filtering, and COTS boards versus custom ASICs. The system design issues of dynamic range, chirp impulse response design, delay line processing latency, and the effect of mismatch between the transmitter and receiver were addressed. The main challenge of the board level design was to meet the digital signal processing computational demands within the inherently short analog delay line latency. This ultimately required developing a custom VLSI signal processing chip. The 1.3 million transistor ASIC chip performs a 1024 tap finite-impulse response (FIR) filter running at an estimated 2 Msps. The configurable architecture of the ASIC allows the number of FIR filter taps to be traded for sampling rate and could be useful in other radar or communication systems.
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