Design techniques of all-digital time integrators for time-mode signal processing

This paper provides a comprehensive treatment of the design techniques of all-digital time integrators for time-mode signal processing (TMSP). A detailed examination of the principle, circuit implementation, operation, constraints, and limitations of time adders constructed from switched delay units (SDUs), dual discharge paths (DDP), and unidirectional gated delay lines (UDGDLs) is provided. It is followed with the presentation of three time registers evolved from the studied time adders and a qualitative comparison of their pros and cons. Finally, time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared.