GPGPU role within a 500 TFLOPS heterogeneous cluster

The outstanding price-performance of GPGPU technology has made it a key architectural engine within a 500 TFLOPS Heterogeneous Cluster being assembled by the Air Force Research Laboratory in Rome, NY. This new machine will likely be the largest interactive HPC in the world and feature $4/GFLOPS overall system performance and 1.5 TFLOPS/KW power efficiency. The heterogeneous aspect of the cluster reflects a combination of roughly 300 TFLOPS performance from 2000 PS3 gaming consoles plus 200 TFLOPS from GPGPUs closely coupled to 84 headnodes of the subclusters within the overall machine. The blend of GPGPUs, Cell processors within the PS3s, and Xeon processors in the headnodes is a deliberate mixing intended to offer an alternative programming environments suiting different applications, or combining on portions of applications. The large DRAM memory and local disk capacity of the multicore Xeon headnode is a familiar environment for handling a wide swath of the application codes with a popular computing environment. But for segments of applications requiring higher performance the Cell and GPGPU architectures are available for acceleration based on large scale parallelization. This talk will discuss programming experiences to date on the GPGPUs, Cells, and Xeons and discuss the attributes of algorithms that would favor each of these aspects of the heterogeneous machine.