高速数字电路中差分蛇形延迟微带线的共模降噪方案

G. Shiue, Y. Tsai, Che-Ming Hsu, Jia-Hung Shiu
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引用次数: 5

摘要

本工作提出了两种降噪方案,即使用强耦合垂直匝走线代替弱耦合垂直匝走线,并增加保护走线来降低弱差分蛇形延迟微带线中的共模噪声。仿真结果表明,采用这两种方法后,共模噪声在时域内的峰间幅值降低了约65%。仿真结果表明,在0.1 ~ 2.7GHz和3.2 ~ 10GHz宽频带的差分蛇形延迟线,其差共模转换幅度减小的频率范围。此外,附加保护走线的差分反射损耗仅在感兴趣的频率上略有降低,但当使用强耦合垂直转弯走线时。然而,使用两种改进方案所获得的差分插入损耗几乎与传统模式相同。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Common-mode noise reduction schemes for differential serpentine delay microstrip line in high-speed digital circuits
This work proposes two noise reduction schemes that use strongly coupled vertical-turn traces as substitute for weakly coupled vertical-turn traces and added guard traces to reduce the common-mode noise in a weakly differential serpentine delay microstrip line. The peak-to-peak amplitude of common-mode noise in the time-domain is reduced by bout 65% using the two methods, according to simulation results. The simulation results demonstrate that the frequency range over which the magnitude of differential-to-common mode conversion is reduced for a differential serpentine delay line with is wide band in the range 0.1∼2.7GHz and 3.2∼10GHz. Furthermore, the differential reflection loss for additional guard traces is only slightly reduced at the frequency of interest, but when strongly coupled vertical-turn traces are used. However, the differential insertion loss achieved using the two improved schemes is almost the same as that of the traditional pattern.
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