{"title":"设计纤维通道织物","authors":"L. Cherkasova, V. Kotov, Tomas Rokicki","doi":"10.1109/ICCD.1995.528832","DOIUrl":null,"url":null,"abstract":"The fibre channel standard, developed by the ANSI X3T9.3 task group, defines a serial I/O channel for interconnecting a number of peripheral devices and computer systems. In this paper we consider how fibre channel switches can be cascaded to form a fibre channel fabric. We begin with an analytical model of topology performance that provides a theoretical upper bound on fabric performance and a method for the practical evaluation of fabric topologies. Next, we present simulation results for a single fibre channel switch having 16 ports and a specific high-level architecture. Finally, we consider cascades of this switch, and discuss some subtleties, such as different routing strategies, deadlocks and unfairness.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Designing fibre channel fabrics\",\"authors\":\"L. Cherkasova, V. Kotov, Tomas Rokicki\",\"doi\":\"10.1109/ICCD.1995.528832\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The fibre channel standard, developed by the ANSI X3T9.3 task group, defines a serial I/O channel for interconnecting a number of peripheral devices and computer systems. In this paper we consider how fibre channel switches can be cascaded to form a fibre channel fabric. We begin with an analytical model of topology performance that provides a theoretical upper bound on fabric performance and a method for the practical evaluation of fabric topologies. Next, we present simulation results for a single fibre channel switch having 16 ports and a specific high-level architecture. Finally, we consider cascades of this switch, and discuss some subtleties, such as different routing strategies, deadlocks and unfairness.\",\"PeriodicalId\":281907,\"journal\":{\"name\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1995.528832\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1995.528832","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The fibre channel standard, developed by the ANSI X3T9.3 task group, defines a serial I/O channel for interconnecting a number of peripheral devices and computer systems. In this paper we consider how fibre channel switches can be cascaded to form a fibre channel fabric. We begin with an analytical model of topology performance that provides a theoretical upper bound on fabric performance and a method for the practical evaluation of fabric topologies. Next, we present simulation results for a single fibre channel switch having 16 ports and a specific high-level architecture. Finally, we consider cascades of this switch, and discuss some subtleties, such as different routing strategies, deadlocks and unfairness.
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