Sparse Bayesian Learning for Directions of Arrival on an FPGA

A direction of arrival (DOA) estimator based on sparse Bayesian learning (SBL) is implemented as a fixed-point arithmetic prototype for an FPGA platform. The prototype is developed from a known algorithm mainly using high-level synthesis with C++ based model specifications. The specialized equations of the algorithm are reduced to arithmetic operations considering the signal flow within the iterative structure. Cholesky factorization is used to solve the matrix inverse problem. Scheduling of each module is done as soon as possible to make use of the parallel FPGA architecture. Different fixed-point word length assumptions are explained and implementation results are shown in terms of resources and latency. Finally, a representative DOA source scenario is simulated and tested with the implemented prototype hardware in the loop. The comparison with a floating-point reference implementation is found to have good agreement with the fixed-point implementation.