使用低延迟log-MAP的turbo解码的VLSI实现注意事项

1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277) Pub Date : 1999-06-22 DOI:10.1109/ICCE.1999.785223

Arun Raghupathy

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引用次数: 11

摘要

软输出Viterbi(参见IEEE J. Sel。区域通讯，vol.16, p.260- 4,1998)算法(SOVA)和对数最大后验概率(log-MAP)算法是turbo解码中常用的算法。我们提出对Viterbi的滑动窗口映射算法进行改进，以进一步减少计算延迟。我们比较了这种低延迟log-MAP算法与滑动窗口log-MAP算法的仿真性能。我们还估计了SOVA、log-MAP和提议的低延迟log-MAP的VLSI实现复杂性。

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VLSI implementation considerations for turbo decoding using a low latency log-MAP

The soft-output Viterbi (see IEEE J. Sel. Areas in Comm., vol.16, p.260-4, 1998) algorithm (SOVA) and the log-maximum a posterior probability (log-MAP) algorithm are commonly used in turbo decoding. We propose to modify the sliding window MAP-algorithm of Viterbi to reduce the computational delay even further. We compare the simulation performance of this low latency log-MAP algorithm with the sliding window log-MAP. We also estimate the VLSI implementation complexities of the SOVA, the log-MAP and the proposed low latency log-MAP.

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来源期刊

1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277)

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