66m / 70mw HS和超低功耗16/spl倍/16 MAC设计，采用TG实现基于web的多媒体系统

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824050

Seung-Min Lee, Jin-H. Chung, Hyung-Seok Yoon, M.M.-O. Lee

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引用次数: 0

摘要

本文研究了在0.6 um CMOS DLP/DLM技术上采用传输门逻辑(TG)实现的基于xor电路的高速(HS)和79 mW低功耗(LP) 16/spl倍/16 MAC性能。结果表明，我们提出的MAC比其他已发表的MAC具有更好的性能，因为它在低功率下没有直流漏电流，并且在高速乘法器前后通过锁存器绕过不必要的开关活动。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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66 M/70 mW HS and ultra-low power 16/spl times/16 MAC design using TG for web-based multimedia system

In this paper a study has been presented on high speed (HS) and 79 mW low power (LP) 16/spl times/16 MAC performance of XOR-based circuits using transmission gate logic (TG) implemented on 0.6 um CMOS DLP/DLM technology. It is shown that our proposed MAC results in better performance than other published MACs due to no DC leakage currents for low power and bypassing unnecessary switching activities with latches before and after the multiplier for high speed.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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