{"title":"快速开关低杂散6-18 GHz混合频率合成器","authors":"S. Biswas, V. Revathi","doi":"10.1109/IMARC.2015.7411404","DOIUrl":null,"url":null,"abstract":"A 6-18 GHz wideband frequency synthesizer with 100 kHz frequency resolution using hybrid Direct Digital Synthesizer (DDS) and Phase Locked Loop (PLL) architecture is presented in this paper. The DDS is used as a reference to the PLL multiplier to extend the frequency range. To achieve fast frequency switching from the overall architecture the PLL is optimized with wide loop bandwidth. But the compromise in doing so is the insufficient rejection of the high close-in DDS spurs by the loop filter. A low spurious noise is achieved in this design by avoiding the bands of DDS frequencies with close-in spurs less than the PLL loop bandwidth using alternate DDS frequencies and consecutive PLL division ratios. Maximum switching time of 6 us and spur levels less than -50 dBc is achieved from the developed module. This module can be used as frequency-agile Local Oscillator (LO) in wideband microwave receivers.","PeriodicalId":307742,"journal":{"name":"2015 IEEE MTT-S International Microwave and RF Conference (IMaRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A fast-switching low-spurious 6–18 GHz hybrid frequency synthesizer\",\"authors\":\"S. Biswas, V. Revathi\",\"doi\":\"10.1109/IMARC.2015.7411404\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 6-18 GHz wideband frequency synthesizer with 100 kHz frequency resolution using hybrid Direct Digital Synthesizer (DDS) and Phase Locked Loop (PLL) architecture is presented in this paper. The DDS is used as a reference to the PLL multiplier to extend the frequency range. To achieve fast frequency switching from the overall architecture the PLL is optimized with wide loop bandwidth. But the compromise in doing so is the insufficient rejection of the high close-in DDS spurs by the loop filter. A low spurious noise is achieved in this design by avoiding the bands of DDS frequencies with close-in spurs less than the PLL loop bandwidth using alternate DDS frequencies and consecutive PLL division ratios. Maximum switching time of 6 us and spur levels less than -50 dBc is achieved from the developed module. This module can be used as frequency-agile Local Oscillator (LO) in wideband microwave receivers.\",\"PeriodicalId\":307742,\"journal\":{\"name\":\"2015 IEEE MTT-S International Microwave and RF Conference (IMaRC)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE MTT-S International Microwave and RF Conference (IMaRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMARC.2015.7411404\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE MTT-S International Microwave and RF Conference (IMaRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMARC.2015.7411404","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast-switching low-spurious 6–18 GHz hybrid frequency synthesizer
A 6-18 GHz wideband frequency synthesizer with 100 kHz frequency resolution using hybrid Direct Digital Synthesizer (DDS) and Phase Locked Loop (PLL) architecture is presented in this paper. The DDS is used as a reference to the PLL multiplier to extend the frequency range. To achieve fast frequency switching from the overall architecture the PLL is optimized with wide loop bandwidth. But the compromise in doing so is the insufficient rejection of the high close-in DDS spurs by the loop filter. A low spurious noise is achieved in this design by avoiding the bands of DDS frequencies with close-in spurs less than the PLL loop bandwidth using alternate DDS frequencies and consecutive PLL division ratios. Maximum switching time of 6 us and spur levels less than -50 dBc is achieved from the developed module. This module can be used as frequency-agile Local Oscillator (LO) in wideband microwave receivers.