10mw 3.6 gbps I/O发射机

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221172

H. Hatamkhani, Koon-Lun Jackie Wong, R. Drost, C. Yang

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引用次数: 39

摘要

本文介绍了一种低功率自端发射机。提出了一种低功耗的阻抗匹配和信道均衡的新架构。测试芯片采用1.8 v电源，采用0.18-/spl mu/m数字CMOS工艺制作。发射机运行速度为3.6 Gbps，功耗为9.66 mW。总变送器面积为0.072 mm/sup /。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 10-mW 3.6-Gbps I/O transmitter

This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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