基于快速运动估计算法的MPEG-4视频LSI容错编解码核

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993085

H. Nakayama, Toshiyuki Yoshitake, Hiroshi Komazaki, Y. Watanabe, H. Araki, Kiyonori Morioka, Jiang Li, Pei-Yan Liu, Shinhaeng Lee, H. Kubosawa, Y. Otobe

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引用次数: 46

摘要

采用0.18 /spl mu/m四金属技术，将基于场景自适应运动估计算法的MPEG-4视频编解码核心集成到5.296/spl次/5.296 mm/sup 2/芯片中。该器件在编解码器操作期间的功耗为131mw, QCIF格式，15帧/秒，13.5 MHz，使用1.5 V电源。

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An MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm

An MPEG-4 video codec core based on a scene-adaptive motion estimation algorithm is integrated into 5.296/spl times/5.296 mm/sup 2/ die using 0.18 /spl mu/m quad-metal technology. The power dissipation during codec operation of the device is 131 mW for QCIF format at 15 frames/s at 13.5 MHz using a 1.5 V supply.

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来源期刊

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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