B. de Jaeger, G. Nicholas, D.P. Borneo, G. Eneman, M. Meuris, M. Heyns
{"title":"高性能高k/金属栅极Ge pmosfet，栅极长度低至125 nm，晕形植入","authors":"B. de Jaeger, G. Nicholas, D.P. Borneo, G. Eneman, M. Meuris, M. Heyns","doi":"10.1109/ESSDERC.2007.4430978","DOIUrl":null,"url":null,"abstract":"Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces VT roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. Ion of 770 muA/mum is attained for Ioff of 8.8 nA/mum at VDD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100degC suggest that Ge will continue to be competitive at realistic logic operating temperatures.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"High Performance High-k/Metal Gate Ge pMOSFETs with gate lengths down to 125 nm and halo implant\",\"authors\":\"B. de Jaeger, G. Nicholas, D.P. Borneo, G. Eneman, M. Meuris, M. Heyns\",\"doi\":\"10.1109/ESSDERC.2007.4430978\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces VT roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. Ion of 770 muA/mum is attained for Ioff of 8.8 nA/mum at VDD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100degC suggest that Ge will continue to be competitive at realistic logic operating temperatures.\",\"PeriodicalId\":103959,\"journal\":{\"name\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2007.4430978\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Performance High-k/Metal Gate Ge pMOSFETs with gate lengths down to 125 nm and halo implant
Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces VT roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. Ion of 770 muA/mum is attained for Ioff of 8.8 nA/mum at VDD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100degC suggest that Ge will continue to be competitive at realistic logic operating temperatures.
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