Analytical Drain Current Model for Amorphous and Polycrystalline Silicon Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

Our previous drain current model for the organic and amorphous InGaZnO thin-film transistors is applied to the amorphous and polycrystalline silicon thin-film transistors. In the drain current model, it is assumed that the trapped carrier concentration is much higher than the free carrier concentration considering both deep trap states and tail trap states in the energy gap of the thin film. The model is valid in both subthreshold and above-threshold regime, and is verified by the available experimental data at different temperatures.