Emulating large designs on small reconfigurable hardware

FPGA based hardware emulation is becoming very popular for checking the functional correctness of designs prior to fabrication. A design is partitioned and mapped on a programmable hardware system that consists of several FPGAs. Typically, as the design size increases, the utilization of FPGA devices tends to fall rapidly. This demands large amounts of hardware resources for emulating large designs. The authors have demonstrated a methodology for mapping huge designs by partitioning, scheduling, and proper controlling through software on small reconfigurable or programmable hardware platforms. They explore the usage of time domain as a viable alternative to space domain for logic emulation. The methodology is demonstrated with real executing examples.