{"title":"一种40nm CMOS输出功率提高的120GHz三倍频器","authors":"Han Cui, Leijun Xu","doi":"10.1109/ICCS51219.2020.9336593","DOIUrl":null,"url":null,"abstract":"This paper introduces a frequency tripler with improved output power in 40nm CMOS process. Low insertion loss and high balanced Baluns are designed for the input and output impedance matching. Meanwhile, LC series resonance is used to suppress the fundamental wave and improve the power of third harmonic wave. When the input power is 10dBm, the peak output power is 3.7dBm, the frequency conversion loss is 6.3dBm and the fundamental suppression ratio is 41dBc. The total DC power consumption is 9.6mW. The 3-dB bandwidth is 12GHz (115.5GHz~127.5GHz).","PeriodicalId":193552,"journal":{"name":"2020 IEEE 2nd International Conference on Circuits and Systems (ICCS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 120GHz Frequency Tripler with Improved Output Power in 40nm CMOS\",\"authors\":\"Han Cui, Leijun Xu\",\"doi\":\"10.1109/ICCS51219.2020.9336593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a frequency tripler with improved output power in 40nm CMOS process. Low insertion loss and high balanced Baluns are designed for the input and output impedance matching. Meanwhile, LC series resonance is used to suppress the fundamental wave and improve the power of third harmonic wave. When the input power is 10dBm, the peak output power is 3.7dBm, the frequency conversion loss is 6.3dBm and the fundamental suppression ratio is 41dBc. The total DC power consumption is 9.6mW. The 3-dB bandwidth is 12GHz (115.5GHz~127.5GHz).\",\"PeriodicalId\":193552,\"journal\":{\"name\":\"2020 IEEE 2nd International Conference on Circuits and Systems (ICCS)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 2nd International Conference on Circuits and Systems (ICCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCS51219.2020.9336593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 2nd International Conference on Circuits and Systems (ICCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS51219.2020.9336593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 120GHz Frequency Tripler with Improved Output Power in 40nm CMOS
This paper introduces a frequency tripler with improved output power in 40nm CMOS process. Low insertion loss and high balanced Baluns are designed for the input and output impedance matching. Meanwhile, LC series resonance is used to suppress the fundamental wave and improve the power of third harmonic wave. When the input power is 10dBm, the peak output power is 3.7dBm, the frequency conversion loss is 6.3dBm and the fundamental suppression ratio is 41dBc. The total DC power consumption is 9.6mW. The 3-dB bandwidth is 12GHz (115.5GHz~127.5GHz).
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