Influence of Stress-Induced-Leakage-Current on Reliability of HfSiOx with EOT>1.5nm and TiN Gate

Looking to reliability of high-k dielectrics, their behavior under electrical stress is very often determined by traps and charges. During the past years a strong focus of the reliability investigation was given to HfO2. However, especially LSTP as well as memory industry is going to use a silicon doped hafnium oxide (HfSiOx). Three different cases of current vs. time dependence are observed with constant voltage stress for HfSiOx. Often the current decreases for short stress times because of charging. This period can be followed by either barrier lowering due to electron detrapping or stress induced leakage current (SILC) (Duschl, 2006). Both mechanisms raise the current level at constant voltage. In the SILC case the increase of leakage can go step wise, whereas for barrier lowering the leakage increases gradually even on small areas. However, although barrier lowering and charging are considered to be reversible by alternating voltage polarity SILC is often not reversible because it introduces damage and high resistance break down spots in the dielectric. During measurement SILC can even remain undetected if barrier lowering and/or charging are dominant. Recently, it was shown that barrier lowering for these HfSiOx is the major contribution to leakage increase over stress time (Duschl, 2006). In the following paper the authors focus on the question if a small SILC contribution behind the dominant measured barrier lowering can become a reliability concern. In a first part major effects of SILC in HfSiOx with EOT>1.5nm and TiN gate are discussed. In a second part we analyze whether SILC damage can be hidden by barrier lowering or not. Finally we are coming to the conclusion, that a sample with leakage increase due to barrier lowering does not exhibit severe SILC in parallel