减少平移旁缓冲有功功率

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI:10.1145/871506.871512

L. Clark, Byungwoo Choi, M. Wilkerson

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引用次数: 20

摘要

降低有功功耗对于电池供电的嵌入式微处理器越来越重要。本文描述了适用于完全关联翻译暂置缓冲区以及其他关联结构和动态寄存器文件的功耗降低技术。Powermill在微处理器上采用0.18 /spl mu/m工艺技术进行了仿真，结果显示节能42%。电路实现，以及。展示了对典型指令组合的适用性的体系结构模拟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Reducing translation lookaside buffer active power

Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 /spl mu/m process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.

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来源期刊

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

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