Extensions to programmable DSP architectures for reduced power dissipation

We present extensions to the programmable DSP architectures for reduced power dissipations. These extensions address power reduction in both external and internal buses, which form a major component of power dissipation in pipelined programmable processors such as DSPs. We present two techniques to reduce power dissipation in the program and data memory address buses, a technique to reduce cross-coupling related power dissipation in the program memory data bus and a technique for reducing power dissipation in the input buses of the ALU. We present results in terms of power savings using these techniques.