基于水平压缩机的平行乘法器

L. Ciminiera
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引用次数: 1

摘要

本文提出了两种新的基于逻辑单元迭代阵列的并行乘法器。两者都能够计算两个n位数字的乘积,延迟为n个单元,而不是经典结构中的2n−1。采用纯卧式压缩机实现高速运行,加速了信号的水平传播;采用合适的阵列结构,缩短了信号的垂直传播。讨论了基于立式压缩机的同类结构的成本和性能优势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Parallel multipliers based on horizontal compressors
Two new implementations of parallel multipliers, based on iterative arrays of logic cells are presented in this paper. Both are able to compute the product of two n bit numbers with a delay of n cells, rather 2n−l as in classical structures. The high speed operation is obtained by using pure horizontal compressors, to accelerate the horizontal signal propagation, and by adopting a suitable array structure, to shorten the vertical signal propagation. The cost and performance advantages over similar structures based on vertical compressors are discussed.
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