D. Walker, R. F. Kaiser, Dylan F. Williams, K. Coakley
{"title":"片上校准的集总元件模型","authors":"D. Walker, R. F. Kaiser, Dylan F. Williams, K. Coakley","doi":"10.1109/ARFTG.2000.327431","DOIUrl":null,"url":null,"abstract":"We examine electrical models for lumped-element impedance standards used in on-wafer network-analyzer calibrations. We illustrate the advantages of using models that are complicated enough to replicate the actual electrical behavior of the lumped standards, but do not have more degrees of freedom than absolutely necessary.","PeriodicalId":166771,"journal":{"name":"56th ARFTG Conference Digest","volume":"165 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Lumped-Element Models for On-Wafer Calibration\",\"authors\":\"D. Walker, R. F. Kaiser, Dylan F. Williams, K. Coakley\",\"doi\":\"10.1109/ARFTG.2000.327431\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We examine electrical models for lumped-element impedance standards used in on-wafer network-analyzer calibrations. We illustrate the advantages of using models that are complicated enough to replicate the actual electrical behavior of the lumped standards, but do not have more degrees of freedom than absolutely necessary.\",\"PeriodicalId\":166771,\"journal\":{\"name\":\"56th ARFTG Conference Digest\",\"volume\":\"165 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"56th ARFTG Conference Digest\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARFTG.2000.327431\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"56th ARFTG Conference Digest","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARFTG.2000.327431","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We examine electrical models for lumped-element impedance standards used in on-wafer network-analyzer calibrations. We illustrate the advantages of using models that are complicated enough to replicate the actual electrical behavior of the lumped standards, but do not have more degrees of freedom than absolutely necessary.
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