A Feedback-Based N-Path Receiver with Reduced Input-Node Harmonic Response

A downconversion receiver employing a switch-based N-path filter with reduced input harmonic response and harmonic translation from around the $3^{\text{rd}}$ and the $5^{\text{th}}$ LO harmonics is presented. The N-path filter employs 8 paths, and is embedded inside a harmonic-selective negative feedback loop. A pulse-width-modulated LO (PWM-LO) is used in the feedback upconverter to reduce the noise injected around the LO fundamental at the input of the N-path downconverter. The architecture is verified in a 65-nm CMOS technology. Approximately 15–18 dB reduction in the $3\mathrm{f}_{LO}$ and $5\mathrm{f}_{LO}$ harmonic response, and 8–10 dB enhancement in harmonic-blocker 3-dB compression is observed in measurement. The use of a PWM-LO, instead of a rectangular clock in the upconverter, improves noise figure by nearly 4 dB.