一个无tdc的ADPLL, 200- 3200mhz范围和3mW功耗，用于22nm CMOS的移动SoC时钟

2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI:10.1109/ISSCC.2012.6176995

N. August, Hyung-Jin Lee, M. Vandepas, R. Parker

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引用次数: 57

摘要

移动SoC设计需要一个低功耗时钟系统，以最大限度地延长电池寿命。主机锁相环是至关重要的，因为它必须保持启用状态，以支持始终打开、始终连接的操作。此外，主机锁相环应提供宽频率范围，低面积，灵活的带宽，未来制造工艺的可扩展性，与电源状态循环时间相比可以忽略不计的锁定时间，以及时钟数字逻辑的可接受周期抖动。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS

Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should offer wide frequency range, low area, flexible bandwidth, scalability to future manufacturing processes, negligible lock time compared to the power-state-cycling time, and acceptable period jitter for clocking digital logic.

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2012 IEEE International Solid-State Circuits Conference

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