使用进位旁路逻辑的快速条件和加法器

AFIPS '65 (Fall, part I) Pub Date : 1899-12-30 DOI:10.1145/1463891.1463968

J. Kruy

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引用次数: 3

摘要

目前各种集成电路类型的逻辑电路可获得的更高速度增加了对更快加法器的需求。增加加法的速度主要有两种方式:(1)通过更有效的逻辑组织，(2)通过使用更快的逻辑元素。

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A fast conditional sum adder using carry bypass logic

The higher speeds obtainable with present day logic circuits of various integrated circuit types increase the need for faster adders. The speed of addition can be increased primarily in two ways: (1) by more efficient logic organization, (2) by using faster logical elements.

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来源期刊

AFIPS '65 (Fall, part I)

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