对延迟到达的数据进行选择和输入选择加法器

Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers Pub Date : 1996-11-03 DOI:10.1109/ACSSC.1996.600853

E. Schwarz, T. McPherson, C. Krygowski

{"title":"对延迟到达的数据进行选择和输入选择加法器","authors":"E. Schwarz, T. McPherson, C. Krygowski","doi":"10.1109/ACSSC.1996.600853","DOIUrl":null,"url":null,"abstract":"An adder is described which is optimized for the case of one of its inputs having a skewed arrival time. If the least significant bits of either of the operands arrives last, a conventional adder will not be able to execute concurrently with any of the prior computation. This paper shows a design which takes advantage of the early arriving bits and performs early computation of the sum. The adder has been fabricated and is part of the exponent unit of a future mainframe computer.","PeriodicalId":270729,"journal":{"name":"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers","volume":"79 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Carry select and input select adder for late arriving data\",\"authors\":\"E. Schwarz, T. McPherson, C. Krygowski\",\"doi\":\"10.1109/ACSSC.1996.600853\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An adder is described which is optimized for the case of one of its inputs having a skewed arrival time. If the least significant bits of either of the operands arrives last, a conventional adder will not be able to execute concurrently with any of the prior computation. This paper shows a design which takes advantage of the early arriving bits and performs early computation of the sum. The adder has been fabricated and is part of the exponent unit of a future mainframe computer.\",\"PeriodicalId\":270729,\"journal\":{\"name\":\"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers\",\"volume\":\"79 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.1996.600853\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1996.600853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

描述了一种针对其中一个输入具有倾斜到达时间的情况进行优化的加法器。如果操作数中任何一个的最低有效位最后到达，则传统的加法器将无法与任何先前的计算并发执行。本文提出了一种利用提前到达比特并提前计算和的设计方案。加法器已制成，是未来大型计算机指数单元的一部分。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Carry select and input select adder for late arriving data

An adder is described which is optimized for the case of one of its inputs having a skewed arrival time. If the least significant bits of either of the operands arrives last, a conventional adder will not be able to execute concurrently with any of the prior computation. This paper shows a design which takes advantage of the early arriving bits and performs early computation of the sum. The adder has been fabricated and is part of the exponent unit of a future mainframe computer.

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Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers

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