Jinkyu Kim, Juyeob Kim, Joohyun Lee, Kyoungrok Cho
{"title":"LTE上行链路的混合基数管道FFT处理器","authors":"Jinkyu Kim, Juyeob Kim, Joohyun Lee, Kyoungrok Cho","doi":"10.1109/ISCE.2016.7797369","DOIUrl":null,"url":null,"abstract":"This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.","PeriodicalId":193736,"journal":{"name":"2016 IEEE International Symposium on Consumer Electronics (ISCE)","volume":"4 31","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A mixed-radix pipeline FFT processor with trivial multiplications for LTE uplink\",\"authors\":\"Jinkyu Kim, Juyeob Kim, Joohyun Lee, Kyoungrok Cho\",\"doi\":\"10.1109/ISCE.2016.7797369\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.\",\"PeriodicalId\":193736,\"journal\":{\"name\":\"2016 IEEE International Symposium on Consumer Electronics (ISCE)\",\"volume\":\"4 31\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Consumer Electronics (ISCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCE.2016.7797369\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Consumer Electronics (ISCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.2016.7797369","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A mixed-radix pipeline FFT processor with trivial multiplications for LTE uplink
This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.