高速图像处理器的研制

K. Nohsoh, K. Akutagawa
{"title":"高速图像处理器的研制","authors":"K. Nohsoh, K. Akutagawa","doi":"10.1109/AAE.1988.47588","DOIUrl":null,"url":null,"abstract":"The authors describe the NIP-III image processor, which can execute a wide variety of general image processing operations for automobile industry manufacturing applications. Sixteen processing units having the same architecture are connected in rows. Individual users can input desired instructions to each unit and also freely change the bus lines linking the units. The processing units are implemented by gate-array large-scale integrated circuits and can perform the arithmetic and logic functions needed for image processing. A high processing speed has been achieved without increasing the size of the circuits. The authors present the hardware architecture of the NIP-III and describe its processing capabilities.<<ETX>>","PeriodicalId":125786,"journal":{"name":"1988., IEEE Workshop on Automotive Applications of Electronics","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Development of a high-speed image processor\",\"authors\":\"K. Nohsoh, K. Akutagawa\",\"doi\":\"10.1109/AAE.1988.47588\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe the NIP-III image processor, which can execute a wide variety of general image processing operations for automobile industry manufacturing applications. Sixteen processing units having the same architecture are connected in rows. Individual users can input desired instructions to each unit and also freely change the bus lines linking the units. The processing units are implemented by gate-array large-scale integrated circuits and can perform the arithmetic and logic functions needed for image processing. A high processing speed has been achieved without increasing the size of the circuits. The authors present the hardware architecture of the NIP-III and describe its processing capabilities.<<ETX>>\",\"PeriodicalId\":125786,\"journal\":{\"name\":\"1988., IEEE Workshop on Automotive Applications of Electronics\",\"volume\":\"101 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1988., IEEE Workshop on Automotive Applications of Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AAE.1988.47588\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1988., IEEE Workshop on Automotive Applications of Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AAE.1988.47588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

作者描述了NIP-III图像处理器,它可以执行各种各样的通用图像处理操作,用于汽车工业制造应用。16个具有相同架构的处理单元成行连接。个人用户可以输入所需的指令到每个单元,也可以自由地改变连接单元的总线线路。处理单元由门阵列大规模集成电路实现,可以执行图像处理所需的算术和逻辑功能。在不增加电路尺寸的情况下实现了高处理速度。作者介绍了NIP-III的硬件结构,并描述了其处理能力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Development of a high-speed image processor
The authors describe the NIP-III image processor, which can execute a wide variety of general image processing operations for automobile industry manufacturing applications. Sixteen processing units having the same architecture are connected in rows. Individual users can input desired instructions to each unit and also freely change the bus lines linking the units. The processing units are implemented by gate-array large-scale integrated circuits and can perform the arithmetic and logic functions needed for image processing. A high processing speed has been achieved without increasing the size of the circuits. The authors present the hardware architecture of the NIP-III and describe its processing capabilities.<>
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信